1. Technical Field
The present invention relates to an organic electroluminescent display (OELD) device, more particularly, to a dual panel type OELD device and a method of fabricating the same.
2. Related Art
An OELD device of new flat panel display devices is a self-emitting type. The OELD device has excellent characteristics of a view angel, a contrast ratio and so on. Also, since the OELD device does not require a backlight assembly, the OELD device has low weight and low power consumption. Moreover, the OELD device has advantages of a high response rate, a low production cost and so on.
FIG. 1 is a circuit diagram showing a pixel region of the OELD device according to the related art. As shown in FIG. 1, a gate line “GL”, a data line “DL”, a power supply line “PSL”, a switching thin film transistor (TFT) “STr”, a storage capacitor “Cst”, a driving TFT “DTr”, and an organic electroluminescent diode “ELD” are formed in the pixel region “P”. The gate line “GL” and the data line “DL” cross each other such that the pixel region “P” is defined, and the power supply line “PSL” is formed to be parallel to the data line “DL”. The switching TFT “STr” is formed at crossing portion of the gate and data line “GL” and “DL”, and the storage capacitor “Cst” is also formed with connected to the switching TFT “STr” and the power supply line “PSL”. The driving TFT “DTr” is connected to the storage capacitor “Cst” and the power supply line “PSL”, and the organic electroluminescent diode “ELD” is connected to the driving TFT “DTr”.
The OELD device emits light by injecting electrons from a cathode and holes from an anode into an emission layer, combining the electrons with the holes, generating an exciton, and transitioning the exciton from an excited state to a ground state. The above-mentioned OELD device including an array device having the switching TFT “STr” and the driving TFT “DTr” and the organic electroluminescent diode “ELD” in a same substrate. The OELD device is fabricated by attaching a first substrate including the array device and the electroluminescent diode “ELD” with a second substrate for encapsulation. However, since the OELD device has a production yield determined by the production yield of the array device and the production yield of the electroluminescent diode “ELD”, the production yield of OELD device is decreased. Accordingly, to resolve these problems, a dual panel type OELD device has been suggested. The dual panel type OELD device is fabricated by attaching a first substrate including the array substrate and a second substrate including the organic electroluminescent diode “ELD”.
FIG. 2 is a plan view of a dual panel type OELD device according to the related art, FIG. 3 is a cross-sectional view showing a pixel region of the dual panel type OELD device, and FIG. 4 is a cross-section view showing a power supply terminal taken along the line IV-IV of FIG. 2.
As shown in FIG. 2, the dual panel type OELD device 1 according to the related art includes a first substrate 10 and a second substrate 60. A display area “D/A” having a plurality of pixel regions “P” and a non-display region (not numbered) having a gate pad area “GPA” and a data pad area “DPA” at a periphery of the display area “DA” are defined in the first substrate 10. In the display region “D/A”, a plurality of gate lines 13 and a plurality of data lines 30, are formed and cross each other to define the plurality of pixel regions “P”. The gate line 13 extends to the gate pad area “GPA” such that an end of the gate line 13 is connected to a gate pad 14 in the gate pad area “GPA”, and the data line 30 extends to the data pad area “DPA” such that an end of the data line 30 is connected to a data pad 31 in the data pad area “DPA”. Though not shown in FIG. 2, the first substrate 10 includes the switching TFT “STr”, the driving TFT “DTr”, and additional components, and the second substrate 60 includes the organic electroluminescent diode “ELD”.
Furthermore, a seal pattern 90 is formed on one of the first and second substrates 10 and 60 to attach the first and second substrate 10 and 60. A power supply terminal “PST” is formed on upper side and lower side of the display area “DA”, and a power supply pad 51 extends from the power supply terminal “PST” and is formed in the gate pad area “GPA” and the data pad area “DPA”.
As shown in FIG. 3, the first substrate 10 and the second substrate 60 face each other and are separated from each other. The driving TFT “DTr” and the switching TFT “STr” (shown in FIG. 1) are formed in an array device area “ADA” of each pixel region “P” (shown in FIG. 2). The driving TFT “DTr” includes a gate electrode 15 on the first substrate 10, a gate insulating layer 20 on the gate electrode 15, a semiconductor layer 23 on the gate insulating layer 20, source and drain electrodes 33 and 36 separated from each other on the semiconductor layer 23, and a passivation layer 40 on the source and drain electrodes 33 and 36. A first connection electrode 45 is formed on the passivation layer 40 and contacts the source electrode 33 through a contact hole 43 of the passivation layer 40.
And the second substrate 60 includes a first electrode 63, a buffer pattern 66, a first spacer 70, an organic luminescent layer 76, a second electrode 80, and a second connection electrode 83. The first electrode 63 is formed on a side facing the first substrate 10, and the buffer pattern 66 is formed on the first electrode 10 at boundary of the plurality of pixel region “P” (of FIG. 2). The first spacer 70 is formed on the buffer pattern 66, and the first spacer 70 and the buffer pattern 66 correspond to the first connection electrode 45 of the first substrate 10. And the organic luminescent layer 76 and the second electrode 80 are sequentially formed on the first electrode 63 in each pixel region “P” (of FIG. 2). The first electrode 63, the second electrode 80 and the organic luminescent layer 76 interposed therebetween compose the organic electroluminescent diode “ELD”. The second connection electrode 83 extends from the second electrode 80 and covers the first spacer 70. When the organic luminescent layer 76 is also formed on the first spacer 70 as in FIG. 3, the second connection electrode 83 covers the organic luminescent layer 76. The second connection electrode 83 contacts the first connection electrode 45 on the first substrate 10 such that the source electrode 33 is electrically connected to the second electrode 80 through the first and second connection electrodes 45 and 83.
FIG. 4 shows a laminated structure of the power supply terminal. As shown in FIG. 4 with FIG. 3, the power supply terminal has the same laminated structure as the driving TFT “DTr” in the pixel region “P”. More particularly, a first metal pattern 16, the gate insulating layer 20, a semiconductor pattern 24, a second metal pattern 38, the passivation layer 40, and a third metal pattern 46 are formed on the first substrate 10. The first metal pattern 16 is formed of a same process as the process of forming the gate electrode 15 and has a same height as the gate electrode 15. The gate insulating layer 20 is formed on the first metal pattern 16. The semiconductor pattern 24 is formed of a same process as the process of forming the semiconductor layer 23 on the gate insulating layer 20 and has a same height as the semiconductor layer 23. The second metal pattern 38 is formed of a same process as the process of forming the source and drain electrodes 33 and 36 on the semiconductor pattern 24 and has a same height as the source and drain electrodes 33 and 36. The passivation layer 40 is formed on the second metal pattern 38. The third metal pattern 46 is formed of a same process as the process of forming the first connection electrode 45 in the area device area “ADA”.
A laminated structure, which is same as the structure of the second substrate 60 in the array device area “ADA”, is formed on the second substrate 60 in the power supply terminal “PST” (shown in FIG. 2). The first electrode 63, the buffer pattern 66, a second spacer 73, an organic luminescent pattern 77, and a third connection electrode 86 are sequentially formed on the second substrate 60. The first electrode 63 is formed on the side facing the first substrate 10, and the buffer pattern 66 and the second spacer 73 is formed on center of the first electrode 63. The organic luminescent pattern 77 is formed on the second spacer 73, and the third connection electrode is formed on the first electrode 63 and covers the second spacer 73 and the organic luminescent pattern 77. The third connection electrode 86 contacts the third metal pattern 46 on the first substrate 10.
An order of laminated layers on the first and second substrate 10 and 60 in the array device area “ADA” of the pixel region “P” and the power supply terminal “PST” is described above. However, since the gate electrode in the array device area “ADA” has a patterned shape and a smaller size than the first metal pattern 16 in the power supply terminal “PST”, the gate insulating layer 20 in the array device area “ADA” has a step difference. However, since laminated layers and patterns on the first substrate in the power supply terminal “PSP” have the same shape, there is no step difference. Because of the step difference, the first connection electrode 45 and the third metal pattern 46 have different heights from the first substrate 10. A second height h2 (shown in FIG. 4) of the third metal pattern 46 from the first substrate 10 is greater than a first height h1 (shown in FIG. 3) of the third connection electrode 45, and thus the gap between the first and second substrates 10 and 60 in pixel region P is different from the gap between the first and second substrates 10 and 60 in power supply terminal “PST”. Moreover, the power supply terminal “PSP” has a greater size than several ten times or several hundred times than each pixel region “P”. Accordingly, both ends of the OELD device 1 have a problem of gap size differences, and the organic electroluminescent diode may not contact the driving TFT.